The present invention is related to a semiconductor device, and more specifically, is directed to a technique capable of being effectively applied to a semiconductor device having a trench-gate structure.
While power transistors are employed in power amplifier circuits, power supply circuits, converters, power protective circuits and the like, since these power transistors may handle high power, both high breakdown voltages and high currents are required. In the case that MISFETs (Metal Insulator Semiconductor Field-Effect Transistors) are used, high-current requirements may be satisfied by increasing channel widths of these MISFETs.
Then, in order to avoid that occupied areas of semiconductor chips are increased by widening such channel widths, for example, mesh-gate structures are employed. In these mesh-gate structures, the gates are arranged in a lattice (grid) shape so as to increase channel widths per unit chip area FETs having such mesh-gate structures are described in, for instance, “SEMICONDUCTOR HANDBOOK” of Pages 429-430 published by OHM-sha Ltd., in 1981.
Conventionally, among these power FETs, such power FETs having planar structures have been employed, since the manufacturing steps thereof are simple and oxide films which constitute gate insulating films can be readily formed. However, when cell sizes are made small in order to lower resistance values of planar FETs, depletion layers of cells located adjacent to each other will extend to contact with each other, so that no current may flow. As a result, even when these planar FETs are tried to be made in very fine manners, resistance values thereof could not be lowered. This is referred to as the “JFET effect.” As a consequence, there is a limitation in lowering resistance values of these planar FETs by being made in very fine manners.
Accordingly, under such a reason that integration degrees of semiconductor cells can be furthermore improved, and in addition, a reason that ON-resistance values can be reduced, such FETs having trench-gate structures without the so-called JFET effect could be conceived. A trench-gate structure is defined as follows: That is, while a conductive layer which will constitute a gate is formed via an insulating film in a trench which is elongated on a major surface of a semiconductor substrate, a deep layer portion of this major surface is employed as a drain region, a surface layer portion of the major surface is employed as a source region, and also a semiconductor layer between the drain region and the source region is used as a channel forming region. This sort of MISFET having the trench-gate structure is disclosed in, for instance, JP-A-8-23092.
Also, Inventors of the present invention could invent the technique capable of preventing the source offset by making the upper surface of the gate conductor layer of the trench-gate structure higher than the major surface of the semiconductor substrate. This technique is opened in JP-A-12-277531. Also, as to FETs having planar structures, JP-A-9-246550 discloses the technique capable of forming the very fine trench in such a manner that the side wall spacer formed on the gate electrode on the substrate is employed so as to exceed the processing limitations.